1. Field of the Invention
This invention relates to the fabrication of integrated circuits (ICs) and in particular to the fabrication of ICs relying on complementary metal oxide on silicon (CMOS) configurations.
2. Art Background
A widely employed IC configuration involves CMOS technology. In this configuration an N- and P-tub are formed as shown at 18 and 19 of FIG. 1. (The N and P tubs have respective electrons and holes as the majority carrier). The gate semiconductor material 20 and 21 is generally n type. The device channel regions 40 and 42 are generally the same carrier types as their respective tubs (although not necessarily), but when inverted during operation conduct through a majority carrier opposite to that of the associated tub. Material having the opposite majority carrier from their underlying tubs are used as source and drain regions 30 and 31. The depth 50 in FIG. 1, of the source and drain junctions are strongly influenced by the device design rule, i.e., the size of the smallest feature critical to the device operation such as the width 60 of the gate in FIG. 1. (The junction depth is defined as the average depth measured in a direction normal to the plane of the silicon substrate (immediately before the first step in source and drain formation) and from this plane to a point where the material changes from n to p type.) As design rules become stricter, e.g., gates become narrower, the depth of the junctions must be correspondingly shallower to maintain acceptable device performance. For example, the junction depth should be no greater than about 0.25 .mu.m for a design rule of 0.75 .mu.m or smaller.
Additionally, for stricter design the decrease in device dimensions produces a strong tendency for the two parasitic bipolar transistors shown in FIG. 2 to produce a catastrophic current flow (denominated latch-up) in response to a transient excursion in operating voltage. Thus, the regions forming these parasitic transistors should be advantageously tailored to lessen this tendency without unacceptably degrading other electrical properties such as leakage current. However, suggested approaches for reducing latch-up tendencies generally add processing complexities (e.g., insulating regions for isolation), unacceptably increase leakage current or increase spacing between devices. Additionally, solely addressing latch-up properties is not enough. To achieve relatively low junction resistance while employing a relatively shallow source and drain, a metal silicide, 64, e.g., tungsten silicide or titanium silicide, overlying junction dopant regions, 62 and 63, is desirable. This region serves as a low resistance current shunt between the shallow junction dopant region and its respective electrical contact.
A variety of attempts have been made to produce relatively shallow source and drain silicided junctions while obtaining a degree of latch-up immunity and maintaining an acceptable leakage current, e.g., a current less than 10.sup.-12 amps/.mu.m.sup.2 for typical CMOS applications. In one method described by Lau et al. (IEEE Transactions on Electronic Devices, ED-33 (9), 1308 (1986)), a precursor to the metal silicide is formed in the junction region. For example, when titanium silicide is desired, titanium is deposited onto the silicon substrate in the junction region. The precursor region is implanted with a suitable dopant; arsenic and/or phosphorus for the n-channel devices in the P-tub and boron entities for p-channel devices in the N-tub. The wafer is then heated to form the metal silicide and to drive a portion of the dopant from the silicide into the underlying region to form the junction dopant regions 62 and 63. Although reportedly this junction has relatively good latch-up immunity, the depth of the resulting junction is significantly greater than desirable for strict design rules.
Another suggested approach for shallow junction fabrication is described by Kobayashi et al. in a paper entitled "Comparison of TiSi.sub.2 and WSi.sub.2 Silicide Shallow Junctions for Sub-micron CMOSs," Abstract of papers, 1986 Symposium on VLSI technology, San Diego, CA. In this method, the precursor region is produced and heated to form the silicide. This silicide is then implanted and heated to induce partial diffusion of the implanted dopant from the silicide region into the underlying silicon to form the junction dopant region. Junction depths of 0.28 and 0.23 .mu.m were obtained for tungsten and titanium silicide, respectively.
The tungsten silicide junction obtained by Kobayashi is, thus, too deep for strict design rules. The titanium silicide region is relatively shallow. However, the dopant profile in the junction (as shown in FIG. 1 of the Kobayashi abstract) increases for at least 700 .ANG. from the silicide/silicon interface into the underlying silicon. If all the implanted dopant had been confined initially in the silicide region, the dopant concentration would monotonically decrease into the silicon from the silicide/silicon interface. Therefore, the profile actually obtained indicates that a significant level of dopant had been implanted below the silicide. Indeed, Kobayashi discusses the desirability of implanting additional arsenic into the underlying silicon to increase dopant concentration, and presumably, to lower the junction resistance. This implantation procedure, however, is undesirable because the resulting implant damage must be removed by high temperature annealing to ensure acceptable leakage currents. As a consequence of the annealing, the junctions are significantly deepened beyond the region desirable for 0.75 .mu.m or smaller design rules.